The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.

The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems

Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability. To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating these descriptions for a software developer could be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). State of the art tools implementing such methodologies have not been designed for the integration with aerospace systems design flows, so significant adaptations could be required to the designer for integrating the hardware implementations with the rest of the design solution. In this paper the integration of a High Level Synthesis design flow in the TASTE framework (http://taste.tuxfamily.org) is presented. TASTE is a set of freely available tools for the development of real time embedded systems developed by the European Space Agency together with a set of its industrial partners. This framework allows to integrate specifications described in different languages (e.g., C, ADA, Simulink, SDL) by means of formal languages (AADL and ASN.1) and to early verify the correctness of the produced solutions. TASTE has been extended with Bambu (http://panda.dei.polimi.it), a tool for the High Level Synthesis developed at Politecnico di Milano. In this way the TASTE users have the possibility to specify which functionalities, provided by means of high level languages such C, have to be implemented in hardware on the FPGA without having to directly provide the hardware implementations. Thanks to the integration of the High Level Synthesis tool indeed, the framework is able not only to produce the hardware implementations, but also to integrate them in the rest of the aerospace system by automatically generating the whole architecture to be implemented on the FPGA. This architecture contains not only the implementation of the hardware accelerators, but also of the components required to transfer the data from and to the rest of the system and to correctly manage their size and endianness. The application of the extended framework to a real case study shows its effective usability

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators

An ASN.1 compiler for embedded/space systems

International audienceThis paper presents ASN1SCC, an open source 2 ASN.1 compiler that generates C/C++ and SPARK/Ada code suitable for low resource environments such as space systems. Moreover, the compiler can produce a test harness that provides full statement coverage in the generated code, and therefore significantly improves its quality. This paper also presents ACN, a new ASN.1 encoding that allows protocol designers to completely control the format of the encoded ASN.1 stream and hence integrate ASN.1 applications with legacy ones. With ASN.1 and ACN, various space protocols such as PUS 3 can be modeled and with the usage of this ASN.1 compiler get automatic implementations of the encoders and decoders. Finally, the ASN.1 compiler can translate an ASN.1/ACN definition into an Interface Control Document (ICD), thus allowing interoperability with projects and people who don't know/use ASN.1

Formal verification of space systems designed with TASTE

Model-Based Systems Engineering (MBSE) is a development approach aiming to build correct-by-construction systems, provided the use of clear, unambiguous and complete models to describe them along the design process. The approach is supported by several engineering tools that automate the development steps, for example the production of code, documentation, test cases and more. TASTE [1] is pragmatic MBSE toolset supported by ESA that encapsulates several technologies to design a system (data modelling, architecture modelling, behaviour modelling/implementation), to automatically generate the binary application(s), and to validate it. One topic left open in TASTE is the formal verification of a system design with respect to specified properties. In this paper we describe our approach based on the IF model-checker [4] to enable the formal verification of properties on TASTE designs. The approach is currently under development in the ESA MoC4Space project

Model-checking for TASTE designed space software systems: results and lessons learned

Model-Based Systems Engineering (MBSE) is an adopted modelling and development approach for correct-by- construction of complex software systems, such as space applications. TASTE [1] is a pragmatic and mature MBSE toolset supported by ESA that enables and provides automation for most of the phases of software system development: (i) heterogeneous system design through several modelling and programming languages (e.g., ASN.1, AADL, SDL, C/C++), (ii) code generation, build and deployment of the binary application(s), (iii) validation through static analysis and simulation, and (iv) formal verification of properties by model-checking. The formal verification capabilities have been recently added to the TASTE toolset in the ESA project Model-Checking for Formal Verification of Space Systems (MoC4Space) and validated on two real-life case studies. Within this paper we report on the results and lessons learned during the project

Concrete aerospace systems

A new trend in space systems is to move from big centralized satellites to smaller, but distributed systems: we call that formation flying, because the idea is to let several satellites achieve complex missions by combining the capabilities of payloads when they are distributed over several physical spacecrafts. For example, the Proba 3 mission will make use of two satellites to study the sun corona. The challenge is big, and will address all the questions that are raised when designing a distributed system: how to take decisions, how to detect faults, how to elect a master without any node knowing for sure the state of the complete system. To be ready to solve these issues, a rock-solid software development process must exist and be supported by tools, so that the system designer can concentrate on what is really new and challenging: the distributed algorithms. This chapter explains how the space sector in Europe tackled this problem of defining a proper development process, and what tools have been developed to deal with the specificities of embedded, heterogeneous systems. We first present the main characteristics of satellites systems and software, then the issues that are faced when developing them, what can be improved, and the concrete solutions that we developed in the scope of the TASTE project to ease the development, integration and validation of on-board software

TASTE: An open-source tool-chain for embedded system and software development

International audienceThis paper presents the results of the past two years of continuous development of the TASTE tool-set. TASTE is a development environment dedicated to embedded, real-time systems and was created under the initiative of the European Space Agency back in 2008, after the completion of a FP6 project called ASSERT. TASTE is free and open source, and is currently used to design small to medium-size systems; it relies on two powerful and complementary modeling languages: ASN.1 and AADL, and comes together with a solid engineering approach. TASTE brings ideas on how a system can be optimally built, by taking and putting together components of heterogeneous nature, and making sure that they run according to their specification and without software hacking introduced during the development. The latest TASTE improvements include several major features such as the integration of VHDL components, the recording/replay of runtime scenarii using message sequence charts, the support of legacy encoding protocols, means to inspect and patch data at runtime, and the generation of systems for additional platforms such as RT Linux (Xenomai). Our graphical front-ends have also been redesigned to offer a better user experience

Exploring the multidimensional representation of individual speech acoustic parameters extracted by deep unsupervised models

International audienceUnderstanding latent representations of speech by unsupervised models enables powerful signal analysis, transformation, and generation. Numerous studies have identified directions of variation of acoustic features such as fundamental frequency or formants in unsupervised models latent spaces, but it is yet not well understood why the variation of such one-dimensional features is often explained by multiple latent dimensions. This paper proposes a methodology for interpreting these dimensions, in the latent space of a variational autoencoder trained on a multi-speaker database

THE ASSERT SET OF TOOLS FOR ENGINEERING (TASTE): DEMONSTRATOR, HW/SW CODESIGN, AND FUTURE

International audienceThis paper reports the results of a project funded by ESA on the use and development of TASTE (The ASSERT Set of Tools for Engineering). TASTE is a set of tools which, ruled by a clear methodology, aims to ease and secure the building of Real-Time Embedded (RTE) systems. The first goal of this project was to evaluate TASTE with an industrial case study, the realization of a satellite demonstrator, so as to confirm its maturity level. Technologies, design and application scenario of the demonstrator were chosen to be very realistic. The second goal of the project was to extend TASTE capabilities by adding hardware/software codesign support to the toolset. Many RTE systems are software and hardware, so adding such codesign support to TASTE broadens the range of targeted systems. For this purpose, basic hardware support was added to the toolset, and the combination between TASTE and SpaceStudio, a full HW/SW codesign environment, has been studied. With this project, we have been able to demonstrate that TASTE could be an answer to the "missing link" between high level system description and equipment design, for systems ranging from simple software-only systems to complex hardware/software systems